High‐speed parallel reconfigurable Fp multipliers for elliptic curve cryptography applications.

Elliptic curve cryptography (ECC) protocols due to higher security strength per bit have been widely accepted and deployed. Finite field multiplication is the most computational intensive operation in data security protocols developed using ECC. This paper presents two high‐speed parallel re‐configurable finite field multipliers: PIMD‐2 and PIMD‐3 over prime field (Fp) for ECC applications. The proposed designs are based on the new novel optimized interleaved multiplication algorithms. This work first identifies room of parallelism by investigating independent operations in the standard interleaved multiplication method and subsequently proposes high‐speed hardware architectures that allow the parallel execution of these operations. Due to the introduced modifications, the critical path delays and clock cycle consumption in the PIMD‐2 and PIMD‐3 designs are reduced simultaneously. The proposed Fp multipliers are synthesized using Xilinx ISE Design Suite and implemented on Virtex‐5 and Virtex‐6 field programmable gate array (FPGA) platforms for common ECC key sizes 160–521 bits. The implementation results reveal that the proposed designs are highly efficient, provided up to 3× improvement in latency with lower area‐delay product and higher throughput per FPGA slice as compared to the state‐of‐the‐art. [ABSTRACT FROM AUTHOR]

Copyright of International Journal of Circuit Theory & Applications is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)