On FPGA implementation in medical secret image sharing with data hiding.

This work proposes an intelligent integration of secret image sharing (SIS) and data hiding to provide integrity and confidentiality on medical images. An n-variable affine Boolean classification is used to generate the shares from the secret medical image and a modification on difference expansion (DE) is proposed to embed the shares on the cover images. The logical operation in Boolean function and modification in binary priority bit plane for DE operation offer simple computation that enables simple hardware realization in Field Programmable Gate Array (FPGA) platform. To implement in hardware, Xilinx ISE design suite 14.5 (device family XC3S50-4PQ208) is used for a secret image of size M×N with 8 bits/pixel. The hardware design offers a maximum frequency of 111.5 MHz and a minimum clock period of 8.965 nanoseconds when the shares of the secret image of size 8×8 is embedded. [ABSTRACT FROM AUTHOR]

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